1. Field of the Invention
The present invention relates to an auto placement and routing device for laying out wiring in a semiconductor integrated circuit, and the semiconductor integrated circuit including the wiring laid out by the auto placement and routing device.
2. Background of the Invention
On the substrate of the semiconductor integrated circuit, a plurality of wires such as a signal line, a source wire and a ground wire are formed. The layout of wiring is determined by the auto placement and routing device. Each wire forms a capacitance between the substrate or the other wire and itself, called a wiring capacitance, as well as having an electrical resistance called a wiring resistance. When a signal is propagated through a signal line, a delay is caused according to a value determined by the product of the wiring resistance and the wiring capacitance of that signal line. If the wiring resistance is disregarded, the delay of the signal is determined by the wiring capacitance.
More specifically, the wiring capacitance equals to a total of a capacitance between the upper or bottom surface of the wire and the substrate (capacitance due to a plane component), a capacitance between the side surface of the wire and the substrate (fringe capacitance), and a capacitance between the adjacent wires (coupling capacitance).
In a semiconductor integrated circuit which was made before the design rule reached a submicron level, the capacitance between the wire and the substrate, especially, the capacitance due to a plane component, formed a large proportion of the wiring capacitance, while the coupling capacitance formed a small proportion thereof. In addition, since the potential of the substrate was unchanged, there was no necessity of considering that the amount of signal delay due to the wiring capacitance may fluctuate with a change in the potential of the substrate.
However, with recent downsizing of the semiconductor integrated circuit, the upper or bottom surface area of the wire becomes small and an interval between the adjacent wires is reduced. This reduces the proportion of the capacitance due to a plane component in the wiring capacitance, while increasing the proportion of the coupling capacitance. To be more specific, the proportion of the coupling capacitance in the whole wiring capacitance has increased to 50% or more. Further, while the potential of the substrate is unchanged, the potential of the wire, especially of the signal line, makes a transition according to the state of a propagated signal. Thus, with the potential transition of the signal line, there occur fluctuations in the amount of signal delay due to the coupling capacitance between that signal line and the adjacent signal line. When the potential transitions of the adjacent two signal lines take place at the same time but in different ways (for example, when the potential of one signal line makes a high to low transition while the potential of the other signal line makes a low to high transition), there arises a problem that the amount of signal delay due to the coupling capacitance between those signal lines is effectively increased.
The fluctuations in the amount of delay in the signal propagation through a signal line is, as previously described, caused by fluctuations in a potential difference between that signal line and the adjacent signal line. However, it can be also considered that the cause is an increase in the coupling capacitance between those signal lines due to the potential transition of the adjacent signal line. In the specification, the coupling capacitance considered with such an increase is referred to as an xe2x80x9ceffective coupling capacitance.xe2x80x9d
Next, timing of a signal transition will be described. In the present semiconductor integrated circuit, a signal propagated through each signal line, in most cases, makes a transition at a time when a reference signal (in general, a clock) makes a transition. The timing of each signal transition in relation to the timing of the clock transition can be considered as a matter of an attribute (signal attribute) of the signal line. For example, a signal line for propagating a signal that makes a transition at the same time that the clock makes a transition, is referred to as a xe2x80x9csignal line having a signal attribute U,xe2x80x9d while a signal line for propagating a signal that makes a transition with a phase difference of a half cycle of the clock as compared with the timing of the clock transition, is referred to as a xe2x80x9csignal line having a signal attribute V.xe2x80x9d In this way of thinking, the potential transitions of the signal lines each having a different signal attribute do not take place at the same time, while the potential transitions of the signal lines having the same signal attribute take place at the same time.
FIG. 17 schematically shows an example of a wiring layout by a conventional auto placement and routing device. For the simplicity of the description, only seven signal lines 1021 to 1027 are shown. Grids 1011 to 10113 are virtual wiring areas placed side by side on the substrate of the semiconductor integrated circuit. The auto placement and routing device allots the signal lines 1021 to 1027 to the grids 1011, 1013, 1015, 1017, 1019, 10111, and 10113, respectively. All the signal lines 1021 to 1027 have the same signal attribute A. Thus, on the substrate of the semiconductor integrated circuit, a plurality of signal lines 1021 to 1027 having the same signal attribute A are placed side by side.
FIG. 18 is a timing chart illustrating a state of each transition of signals propagated through the signal lines 1021 to 1027, respectively. Since the signal lines 1021 to 1027 have the same signal attribute A, all the signals propagated through those signal lines 1021 to 1027 make transitions at an observed time T100. In this case, the signals propagated through the signal lines 1021 to 1023 and 1025 to 1027 make transitions from their low level (e.g., 0V) to their high level (e.g., 2.5 V), while the signal propagated through the signal line 1024 makes a high to low transition. With the signal transitions, the potentials of the signal lines 1021 to 1027 also make transitions.
Noting the signal lines 1023 and 1024, we will now describe fluctuations in the effective coupling capacitance accompanied by the potential transitions of the signal lines. As shown in FIG. 18, before the observed time T100, the potential of the signal line 1023 was 0V and the potential of the signal line 1024 was 2.5 V. That is, a potential difference between those signal lines was 2.5 V. However, the potential transitions of the signal lines 1023 and 1024 from 0 to 2.5 V and from 2.5 to 0 V, respectively, at the observed time T100 causes an apparent potential difference of 5 V therebetween. That is, at the moment of the potential transitions, the potential difference is increased to twice the value before the transitions. This doubles the effective coupling capacitance between the signal lines 1023 and 1024 as compared with the value before the potential transitions. Since the signal lines 1023 and 1024 are allotted at two grid intervals as shown in FIG. 17, an increase in the effective coupling capacitance accompanied by the potential transitions of those signal lines is expressed by C/2 where C is a coefficient of the coupling capacitance.
Since the signal lines 1021 to 1027 have the same signal attribute A as previously described, the signals propagated through the signal lines 1021 to 1027, respectively, make transitions at the same observed time T100. Thus, the increase in the effective coupling capacitance accompanied by the potential transitions of the signal lines takes place not only between the signal lines 1024 and 1023 but also between the signal line 1024 and each of the other signal lines 1021, 1022, 1025, 1026, 1027. FIG. 19 shows such an increase in the effective coupling capacitance between the signal line 1024 and each of the other signal lines 1021 to 1023 and 1025 to 1027. In accordance with a grid interval between the signal line 1024 and each of the signal lines 1021 to 1023, 1025 to 1027, the effective coupling capacitances are increased by C/6 between the signal line 1024 and each of the signal lines 1021 and 1027, by C/4 between the signal line 1024 and each of the signal lines 1022 and 1026, and by C/2 between the signal line 1024 and each of the signal lines 1023 and 1025. Thus, the total increase in the effective coupling capacitances equals to C/6+C/4+C/2+C/2+C/4+C/6=11C/6.
In this manner, the conventional auto placement and routing device lays out wiring only with consideration for a reduction in the total wire length or a reduction in the wiring area. That is, no consideration is given for the increase in the effective coupling capacitance due to the potential transition of the adjacent wire.
FIG. 20 is a timing chart illustrating an increase in the amount of signal delay. This drawing corresponds to the extraction of waveforms of the signal lines 1023 to 1025 shown in FIG. 18. The increase in the effective coupling capacitance causes an overshoot 103 on the waveform of the signal line 1024. Thus, the signal transition through the signal line 1024 is delayed for a time D, as compared with the signal transitions through the signal lines 1023 and 1025. In this manner, the conventional auto placement and routing device has a problem that the increase in the effective coupling capacitance causes the increase in the amount of delay in the signal propagation through each signal line.
As the scale of the circuit increases, the wire length is necessarily increased and thus a load such as a parasitic capacitance and a parasitic resistance is increased. This becomes a drawback to high speed and high reliability of the semiconductor integrated circuit.
A first aspect of the present invention is directed to an auto placement and routing device. The device comprises: net list input means for inputting a net list that gives connection information as to a circuit which is formed by connecting elements by a plurality of wires including a plurality of signal lines; and layout data generation means for generating layout data with which each of the plurality of wires and each of the elements are allotted on a substrate to form the circuit. The net list includes information as to timing of each potential transition of the plurality of signal lines. The layout data generation means allots a wire the potential of which does not make a transition at a first time for a wire adjacent to one side of a first signal line the potential of which makes a transition at the first time, on the basis of the information as to timing in the net list.
According to a second aspect of the present invention, in the auto placement and routing device of the first aspect, the wire the potential of which does not make a transition at the first time is a second signal line the potential of which makes a transition at a second time that is different from the first time.
According to a third aspect of the present invention, in the auto placement and routing device of the second aspect, the layout data generation means allots a third signal line the potential of which makes a transition at the second time for a wire adjacent to the other side of the first signal line.
According to a fourth aspect of the present invention, in the auto placement and routing device of the second aspect, the layout data generation means allots a fourth signal line the potential of which makes a transition at the first time for a wire adjacent to the other side of the first signal line.
According to a fifth aspect of the present invention, in the auto placement and routing device of the fourth aspect, the layout data generation means sets an interval between the first signal line and the fourth signal line wider than an interval between the first signal line and the second signal line.
According to a sixth aspect of the present invention, in the auto placement and routing device of the first aspect, the wire the potential of which does not make a transition at the first time is either a source wire or a ground wire.
According to a seventh aspect of the present invention, in the auto placement and routing device of the sixth aspect, the layout data generation means allots either a source wire or a ground wire for a wire adjacent to the other side of the first signal line.
According to an eighth aspect of the present invention, in the auto placement and routing device of the sixth aspect, the layout data generation means allots a fifth signal line the potential of which makes a transition at the first time or at a second time that is different from the first time, for a wire adjacent to the other side of the first signal line. The layout data generation means further sets an interval between the first signal line and the fifth signal line wider than an interval between the first signal line and either the source wire or the ground wire.
According to a ninth aspect of the present invention, in the auto placement and routing device of the sixth aspect, the net list includes information as to delays in the signal propagation through each of the plurality of signal lines, and the layout data generation means sets one of the plurality of signal lines that is especially susceptible to influences of signal delay, as the first signal, on the basis of the information as to signal delay.
According to a tenth aspect of the present invention, in the auto placement and routing device of the first aspect, each potential of the plurality of signal lines makes a transition in synchronization with the transition of a reference signal, and the information as to timing in the net list includes a tolerable time difference in the potential transitions between the reference signal and each of the plurality of signal lines.
An eleventh aspect of the present invention is directed to a semiconductor integrated circuit comprising a plurality of wires placed side by side. The plurality of wires including a first signal line the potential of which makes a transition at a first time. A wire adjacent to one side of the first signal line is a wire the potential of which does not make a transition at the first time.
According to a twelfth aspect of the present invention, in the semiconductor integrated circuit of the eleventh aspect, the wire the potential of which does not make a transition at the first time is a second signal line the potential of which makes a transition at a second time that is different from the first time.
According to a thirteenth aspect of the present invention, in the semiconductor integrated circuit of the twelfth aspect, a wire adjacent to the other side of the first signal line is a third signal line the potential of which makes a transition at the second time.
According to a fourteenth aspect of the present invention, in the semiconductor integrated circuit of the twelfth aspect, a wire adjacent to the other side of the first signal line is a fourth signal line the potential of which makes a transition at the first time.
According to a fifteenth aspect of the present invention, in the semiconductor integrated circuit of the fourteenth aspect, an interval between the first signal line and the fourth signal line is wider than an interval between the first signal line and the second signal line.
According to a sixteenth aspect of the present invention, in the semiconductor integrated circuit of the eleventh aspect, the wire the potential of which does not make a transition at the first time is either a source wire or a ground wire.
According to a seventeenth aspect of the present invention, in the semiconductor integrated circuit of the sixteenth aspect, a wire adjacent to the other side of the first signal line is either a source wire or a ground wire.
According to an eighteenth aspect of the present invention, in the semiconductor integrated circuit of the sixteenth aspect, a wire adjacent to the other side of the first signal line is a fifth signal line the potential of which makes a transition at the first time or at a second time that is different from the first time, and an interval between the first signal line and the fifth signal line is wider than an interval between the first signal line and either the source wire or the ground wire.
According to a nineteenth aspect of the present invention, in the semiconductor integrated circuit of the sixteenth aspect, the first signal line is one of the plurality of signal lines that is especially susceptible to influences of signal delay.
In the device of the first aspect, the potential transition of the wire adjacent to the other side of the first signal line does not take place at the first time when the potential transition of the first signal line takes place. This prevents, at the first time, an increase in the coupling capacitance between the first signal line and the wire due to the potential transition of that wire.
In the device of the second aspect, while the potential transition of the first signal line takes place at the first time, the potential transition of the second signal line adjacent to one side of the first signal takes place at the second time. This prevents, at the first time, an increase in the coupling capacitance between the first signal line and the second signal line due to the potential transition of the second signal line.
In the device of the third aspect, while the potential transition of the first signal line takes place at the first time, the potential transition of the third signal line adjacent to the other side of the first signal takes place at the second time. This prevents, at the first time, an increase in the coupling capacitance between the first signal line and the third signal line due to the potential transition of the third signal line.
In the device of the fourth aspect, the potential transition of the fourth signal line which is adjacent to the other side of the first signal line takes place at the first time as the potential transition of the first signal line. This prevents, at the second time, an increase in the coupling capacitance between the first signal line and the fourth signal line due to the potential transition of the fourth signal line.
In the device of the fifth aspect, the layout data generation means sets the interval between the first signal line and the fourth signal line the potentials of which make transitions at the first time, wider than the interval between the first signal line and the second signal line the potentials of which make transitions at different times. This relieves, at the first time, an increase in the coupling capacitance between the first signal line and the fourth signal line due to the potential transition of the fourth signal line.
In the device of the sixth aspect, the layout data generation means allots either the source wire or the ground wire for a wire adjacent to one side of the first signal line. Since the potential of the source wire or the ground wire does not make a transition, there occurs no fluctuation in the coupling capacitance between the first signal line and either the ground wire or the source wire.
In the device of the seventh aspect, the layout data generation means allots either the source wire or the ground wire not only for a wire adjacent to one side of the first signal line but also for a wire adjacent to the other side of the first signal line. Thus, the first signal line is sandwiched between the source wires or the ground wires. This prevents fluctuations in the coupling capacitance.
In the device of the eighth aspect, the layout data generation means sets the interval between the first signal line and the fifth signal line wider than the interval between the first signal line and either the source wire or the ground wire. This relieves an increase in the coupling capacitance between the first signal line and the fifth signal line due to the potential transition of the fifth signal line.
In the device of the ninth aspect, the layout data generation means sets one of the plurality of signal lines that is especially susceptible to influences of signal delay, as a first signal line. Then, an increase in the coupling capacitance of that signal line is appropriately reduced by the invention according to the sixth aspect. This appropriately suppresses a delay in the signal propagation through that signal line.
In the device of the tenth aspect, when the time difference in the potential transitions between the reference signal and the signal line is within a tolerable range, the layout data generation means can generate layout data, regarding the potential transition of that signal line as being synchronized with the transition of the reference signal. This indicates that the invention according to the first aspect is applicable to the actual form.
In the circuit of the eleventh aspect, the potential transition of the wire adjacent to one side of the first signal line does not take place at the first time when the potential transition of the first signal line takes place. This prevents, at the first time, an increase in the coupling capacitance between the first signal line and that wire due to the potential transition of that wire.
In the circuit of the twelfth aspect, while the potential transition of the first signal line takes place at the first time, the potential transition of the second signal adjacent to one side of the fist signal line takes place at the second time. This prevents, at the second time, an increase in the coupling capacitance between the first signal line and the second signal line due to the potential transition of the second signal line.
In the circuit of the thirteenth aspect, while the potential transition of the first signal line takes place at the first time, the potential transition of the third signal line adjacent to the other side of the first signal line takes place at the second time. This prevents, at the first time, an increase in the coupling capacitance between the first signal line and the third signal line due to the potential transition of the third signal line.
In the circuit of the fourteenth aspect, the potential transition of the fourth signal line adjacent to the other side of the first signal line takes place at the first time as the potential transition of the first signal line. This prevents, at the second time, an increase in the coupling capacitance between the first signal line and the fourth signal line due to the potential transition of the fourth signal line.
In the circuit of the fifteenth aspect, the interval between the first signal line and the fourth signal line the potentials of which make transitions at the first time, is wider than the interval between the first signal line and the second line the potentials of which make transitions at different times. This relieves, at the first time, an increase in the coupling capacitance between the first signal line and the fourth signal line due to the potential transition of the fourth signal line.
In the circuit of the sixteenth aspect, the first signal line is adjacent to either the source wire or the ground wire. Since the potential of the source wire or the ground wire does not make a transition, there occurs no fluctuation in the coupling capacitance between the first signal line and either the source wire or the ground wire.
In the circuit of the seventeenth aspect, the first signal line is sandwiched between the source wires or the ground wires. This prevents fluctuations in the coupling capacitance.
In the circuit of the eighteenth aspect, the interval between the first signal line and the fifth signal line is wider than the interval between the first signal line and either the source wire or the ground wire. This relieves an increase in the coupling capacitance between the first signal line and the fifth signal line due to the potential transition of the fifth signal line.
In the circuit of the nineteenth aspect, one of the plurality of signal lines that is especially susceptible to influences of signal delay is adopted as the first signal line.
Thus, an increase in the coupling capacitance of that signal line is reduced by the invention according to the sixteenth aspect. This appropriately suppresses a delay in the signal propagation through that signal line.
An object of the present invention is to provide an auto placement and routing device for laying out wiring with consideration for influences of the increase in the effective coupling capacitance, and to obtain a semiconductor integrated circuit suitable for high speed and high reliability by laying out the wiring by the auto placement and routing device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.